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H8SX/1663R Datasheet(PDF) 958 Page - Renesas Technology Corp

Part # H8SX/1663R
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 958 Page - Renesas Technology Corp

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 926 of 1468
REJ09B0412-0200
19.5.2
Multiprocessor Serial Data Reception
Figure 19.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
19.15 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDR
value
0D0
D1
D71
1
0D0
D1
D7
01
1
1
Data (ID1)
Start
bit
MPB
Stop
bit
Start
bit
Data (Data 1)
MPB
Stop
bit
Data (ID2)
Start
bit
Stop
bit
Start
bit
Data (Data 2)
Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
If not this station's ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station's ID
MPIE
RDR
value
0D0
D1
D71
1
0D0
D1
D7
01
1
1
MPB
MPB
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
Matches this station's ID,
so reception continues, and
data is received in RXI
interrupt processing routine
MPIE bit set to 1
again
ID2
(b) Data matches station's ID
Data 2
ID1
MPIE = 0
MPIE = 0
Figure 19.15 Example of SCI Operation for Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)



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