H8SXSLASH1663R datasheet(957/1504 Pages) RENESAS

957 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 925 of 1468

REJ09B0412-0200

19.5.1

Multiprocessor Serial Data Transmission

Figure 19.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID

transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission

cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same

as those in asynchronous mode.

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted?

TEND = 1

Break output?

Clear TDRE flag to 0

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin. After the TE bit is set

to 1, a 1 is output for one frame,

and transmission is enabled.

[2] SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to 0.

However, the TDRE flag is

checked and cleared

automatically when the DMAC or

DTC is initiated by a transmit

data empty interrupt (TXI)

request and writes data to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the

port to 1, clear DR to 0, and then

clear the TE bit in SCR to 0.

Figure 19.14 Sample Multiprocessor Serial Transmission Flowchart

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