H8SXSLASH1663R datasheet(985/1504 Pages) RENESAS

985 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 953 of 1468

REJ09B0412-0200

19.10

Usage Notes

19.10.1

Module Stop Function Setting

Operation of the SCI can be disabled or enabled using the module stop control register. The initial

setting is for operation of the SCI to be halted. Register access is enabled by clearing the module

stop state. For details, see section 28, Power-Down Modes.

19.10.2

Break Detection and Processing

When framing error detection is performed, a break can be detected by reading the RxD pin value

directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the

PER flag may also be set. Note that, since the SCI continues the receive operation even after

receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.

19.10.3

Mark State and Break Detection

When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and

level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high

level) or send a break during serial data transmission. To maintain the communication line in mark

state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0

at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break

during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the

TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the

TxD pin becomes an I/O port, and 0 is output from the TxD pin.

19.10.4

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is

cleared to 0.

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