H8SXSLASH1663R datasheet(1000/1504 Pages) RENESAS

1000 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 968 of 1468

REJ09B0412-0200

20.3.1

Interrupt Flag Register 0 (IFR0)

IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status

information required by the application. When an interrupt source is generated, the corresponding

bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates

an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.

However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.

Bit

Bit Name

Initial Value

R/W

BRST

R/W

EP1 FULL

EP2 TR

R/W

EP2 EMPTY

SETUP TS

R/W

EP0o TS

R/W

EP0i TR

R/W

EP0i TS

R/W

Bit

Bit Name

Initial

Value

R/W

Description

BRST

R/W

Bus Reset

This bit is set to 1 when a bus reset signal is detected on

the USB bus.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

EP1 FULL

EP1 FIFO Full

This bit is set when endpoint 1 receives one packet of

data successfully from the host, and holds a value of 1

as long as there is valid data in the FIFO buffer.

This is a status bit, and cannot be cleared.

EP2 TR

R/W

EP2 Transfer Request

This bit is set if there is no valid transmit data in the FIFO

buffer when an IN token for endpoint 2 is received from

the host. A NACK handshake is returned to the host until

data is written to the FIFO buffer and packet

transmission is enabled.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

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