H8SXSLASH1663R datasheet(1001/1504 Pages) RENESAS

1001 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 969 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

EP2 EMPTY

EP2 FIFO Empty

This bit is set when at least one of the dual endpoint 2

transmit FIFO buffers is ready for transmit data to be

written.

This is a status bit, and cannot be cleared.

SETUP TS

R/W

Setup Command Receive Complete

This bit is set to 1 when endpoint 0 receives successfully

a setup command requiring decoding on the application

side, and returns an ACK handshake to the host.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

EP0o TS

R/W

EP0o Receive Complete

This bit is set to 1 when endpoint 0 receives data from

the host successfully, stores the data in the FIFO buffer,

and returns an ACK handshake to the host.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

EP0i TR

R/W

EP0i Transfer Request

This bit is set if there is no valid transmit data in the

FIFO buffer when an IN token for endpoint 0 is received

from the host. A NACK handshake is returned to the

host until data is written to the FIFO buffer and packet

transmission is enabled.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

EP0i TS

R/W

EP0i Transmit Complete

This bit is set when data is transmitted to the host from

endpoint 0 and an ACK handshake is returned.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

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