H8SXSLASH1663R datasheet(1004/1504 Pages) RENESAS

1004 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 972 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

SURSF

R/W

Suspend/Resume Detection

This bit is set to 1 when the state changed from normal

to suspended state or vice versa. The corresponding

interrupt output is RESUME, USBINTN2, and

USBINTN3.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

CFDN

R/W

End Point Information Load End

This bit is set to 1 when writing data in the endpoint

information register to the EPIR register ends (load

end). This module starts the USB operation after the

endpoint information is completely set.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

—

Reserved

This bit is always read as 0. The write value should

always be 0.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

SETC

R/W

Set_Configuration Command Detection

When the Set_Configuration command is detected, this

bit is set to 1.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

SETI

R/W

Set_Interface Command Detection

When the Set_Interface command is detected, this bit

is set to 1.

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure to

read the flag after writing 0 to it.)

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