H8SXSLASH1663M datasheet(1096/1504 Pages) RENESAS

1096 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1064 of 1468

REJ09B0412-0200

21.5

Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK detection, STOP recognition, and arbitration lost. Table 21.3 shows the contents of each

interrupt request.

Table 21.3

Interrupt Requests

Interrupt Request

Abbreviation

Interrupt Condition

Transmit Data Empty

TXI

(TDRE = 1)

⋅ (TIE = 1)

Transmit End

TEI

(TEND = 1)

⋅ (TEIE = 1)

Receive Data Full

RXI

(RDRF = 1)

⋅ (RIE = 1)

Stop Recognition

STPI

(STOP = 1)

⋅ (STIE = 1)

NACK Detection

Arbitration Lost

NAKI

{(NACKF = 1)

+ (AL = 1)} ⋅ (NAKIE = 1)

When one of the interrupt conditions in table 21.3 is 1 and the I bit in CCR is 0, the CPU executes

interrupt exception handling. Clear the interrupt sources during interrupt exception handling. Note

that the TDRE and TEND bits are automatically cleared to 0 by writing data to ICDRT, and the

RDRF bit is cleared to 0 by reading ICDRR. In particular, the TDRE bit can be set again at the

same time as data are for transmission written to ICDRT, and 1 extra byte can be transmitted if the

TDRE is again cleared to 0.

21.6

Bit Synchronous Circuit

This module has a possibility that the high-level period is shortened in the two states described

below.

In master mode,

• When SCL is driven low by the slave device

• When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or

pull-up resistance)

Therefore, this module monitors SCL and communicates bit by bit in synchronization.

Figure 21.18 shows the timing of the bit synchronous circuit, and table 21.4 shows the time when

SCL output changes from low to Hi-Z and the period which SCL is monitored.

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