H8SXSLASH1663M datasheet(1098/1504 Pages) RENESAS

1098 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1066 of 1468

REJ09B0412-0200

3. Restriction in transfer rate setting value in multi-master mode

When the transfer rate of I

2C transfer of this LSI is slower than that of other master, the SCL

signal the width of which is unexpected may be output. To avoid this phenomenon, set a

transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of I

transfer rate. For example, if the fastest rate of other masters is 400 kbps, the I

2C transfer rate

of this LSI should be 223 kbps (= 400/1.8) or more.

4. Restriction in bit manipulation when the MST and TRS bits are set in multi-master mode

When the MST and TRS bits are set to master slave mode by manipulating these bits

sequentially, the conflict state occurs as follows according to the timing that arbitration is lost;

The AL bit in ICSR is set to 0, and set to master mode (MST = 1, TRS = 1). There are the

following methods to avoid this phenomenon.

•

In multi-master mode, set the MST and TRS bits by MOV instruction.

•

When arbitration is lost, confirm that the MST and TRS bits are set to 0. If these bits are

set to other than 0, set these bits to 0.

5. Notes on master receive mode

In master receive mode, the RDRF bit is set to 0 at the eighth rising clock, the SCL signal is

pulled to “Low” state. When ICDRR is read near at the eighth falling clock, the SCL signal

level is released and the ninth clock is outputted by fixing the eighth clock of receive data to

“Low” state. Reading ICDRR is not required. As a result, the failure to receive data occurs.

There are the following methods to avoid this phenomenon.

•

In master receive mode, read ICDRR by the eighth rising clock.

•

In master receive mode, set the RCVD bit to 1 and process the bit by the communication

of every one byte.

6. Setting of the module stop function

Operation of the IIC2 can be disabled or enabled using the module stop control register. The

initial setting is for operation of the IIC2 to be halted. Register access is enabled by clearing

module stop state. For details, see section 28, Power-Down Modes.

H8SX/1663M Datasheet(PDF) 1098 Page - Renesas Technology Corp