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M32C/86 Datasheet(PDF) 372 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 372 Page - Renesas Technology Corp |
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372 / 505 page  Page 349 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 23. CAN Module ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M CANi Message Slot j Control Register (i=0,1, j=0 to 15)(1) Symbol Address After Reset(2) C0MCTL0 to C0MCTL3 023016(3), 023116(3), 023216(3), 023316(3) 0016 C0MCTL4 to C0MCTL7 023416(3), 023516, 023616, 023716 0016 C0MCTL8 to C0MCTL11 023816(4), 023916(4), 023A16(4), 023B16(4) 0016 C0MCTL12 to C0MCTL15 023C16(4), 023D16, 023E16, 023F16 0016 C1MCTL0 to C1MCTL3 02B016(5), 02B116(5), 02B216(5), 02B316(5) 0016 C1MCTL4 to C1MCTL7 02B416(5), 02B516, 02B616, 02B716 0016 C1MCTL8 to C1MCTL11 02B816(6), 02B916(6), 02BA16(6), 02BB16(6) 0016 C1MCTL12 to C1MCTL15 02BC16(6), 02BD16, 02BE16, 02BF16 0016 When receive, NEWDATA When transmit, SENTDATA When receive, INVALDATA When transmit, TRMACTIVE MSGLOST REMACTIVE Receive Complete Flag Transmit Complete Flag Receiving Flag Transmitting Flag In modes other than BasicCan mode 0: Data frame 1: Remote frame In BasicCan mode 0: Receives the data frame (status) 1: Receives the remote frame (status) Overwrite Flag(7) Remote Frame Transmit/Receive Status Flag When receiving 0: Not received(4) 1: Receive complete When transmitting 0: Not transmitted(4) 1: Transmit complete When receiving 0: Except storing received data 1: Stores received data Bit Name Function Bit Symbol 0: No overrun error occurs 1: Overrun error occurs When transmitting 0: Except transmitting 1: Transmittting b7 b6 b5 b4 b3 b2 b1 b0 RW RW RO RW RO RSPLOCK REMOTE TRMREQ RECREQ 0: Enables automatic answering of the remote frame 1: Disables automatic answering of the remote frame 0: Transmits/receives the data frame 1: Transmits/receives the remote frame 0: No request to receive the frame 1: Request to receive the frame 0: No request to transmit the frame 1: Request to transmit the frame Automatic Answering Disable Mode Select Bit Remote Frame Set Bit Receive Request Bit Transmit Request Bit RW RW RW RW NOTES: 1. The CiMCTLj register can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to "0" (message slot control register and single-shot register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0". 3. The C0MCTL0 to C0MCTL4 registers each share addresses with the C0LMAR0 to C0LMAR4 registers. 4. The C0MCTL8 to C0MCTL12 registers each share addresses with the C0LMBR0 to C0LMBR4 registers. 5. The C1MCTL0 to C1MCTL4 registers each share addresses with the C1LMAR0 to C1LMAR4 registers. 6. The C1MCTL8 to C1MCTL12 registers each share addresses with the C1LMBR0 to C1LMBR4 registers. 7. Set to "0" by program. If it is set to "1", the value before setting to "1" remains. 23.1.20 CANi Message Slot j Control Register (CiMCTLj Register) (i=0,1, j=0 to 15) Figure 23.29 C0MCTL0 to C0MCTL15 Registers and C1MCTL0 to C1MCTL15 Registers |
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