M32CSLASH86 datasheet(369/505 Pages) RENESAS

369 / 505 page

Page 346

23. CAN Module

)

(

CANi Global Mask Register Extended ID2(1)

CANi Local Mask Register A Extended ID2(1)

CANi Local Mask Register B Extended ID2(1) (i=0, 1)

EID0M

EID1M

EID2M

EID3M

EID4M

EID5M

(b7 - b6)

Extended ID0

0: No ID is verified

1: ID is verified

Extended ID1

Extended ID2

Extended ID3

Extended ID4

Extended ID5

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. The CiGMR4, CiLMAR4 and CiLMBR4 registers can be accessed only when the BANKSEL bit in

the CiCTLR1 register is set to "1" (mask register selected).

2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".

3. The C0LMAR4 register shares the same address with the C0MCTL4 register.

4. The C1LMAR4 register shares the same address with the C1MCTL4 register.

5. The C0LMBR4 register shares the same address with the C0MCTL12 register.

6. The C1LMBR4 register shares the same address with the C1MCTL12 register.

Symbol

Address

After Reset(2)

C0GMR4, C1GMR4

022C16, 02AC16

XX00 00002

C0LMAR4, C1LMAR4

023416(3), 02B416(4)

XX00 00002

C0LMBR4, C1LMBR4

023C16(5), 02BC16(6)

XX00 00002

Figure 23.26 C0GMR4, C0LMAR4 and C0LMBR4 Registers

C1GMR4, C1LMAR4 and C1LMBR4 Registers

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