M32CSLASH86 datasheet(366/505 Pages) RENESAS

366 / 505 page

Page 343

23. CAN Module

)

(

Figure 23.23 C0GMR1, C0LMAR1 and C0LMBR1 Registers

C1GMR1, C1LMAR1 and C1LMBR1 Registers

CANi Global Mask Register Standard ID1(1)

CANi Local Mask Register A Standard ID1(1)

CANi Local Mask Register B Standard ID1(1) (i=0, 1)

Symbol

Address

After Reset(2)

C0GMR1, C1GMR1

022916, 02A916

XX00 00002

C0LMAR1, C1LMAR1

023116(3), 02B116(4)

XX00 00002

C0LMBR1, C1LMBR1

023916(5), 02B916(6)

XX00 00002

Standard ID0

0: No ID is verified

1: ID is verified

Standard ID1

Standard ID2

Standard ID3

Standard ID4

Standard ID5

SID0M

SID1M

SID2M

SID3M

SID4M

SID5M

(b7 - b6)

Bit Name

Function

Bit

Symbol

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

NOTES:

1. The CiGMR0, CiLMAR0 and CiLMBR0 registers can be accessed only when the BANKSEL bit in

the CiCTLR1 register is set to "1" (mask register selected).

2. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after

reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".

3. The C0LMAR1 register shares the same address with the C0MCTL1 register.

4. The C1LMAR1 register shares the same address with the C1MCTL1 register.

5. The C0LMBR1 register shares the same address with the C0MCTL9 register.

6. The C1LMBR1 register shares the same address with the C1MCTL9 register.

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