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M32C/86 Datasheet(PDF) 227 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 227 Page - Renesas Technology Corp |
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227 / 505 page  Page 204 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (UART) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M P SP ST SP ST P TxDi (no inverse) Transfer Clock "H" "L" "H" "L" (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse) TxDi (inverse) "H" "L" Transfer Clock "H" "L" (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) NOTES: 1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ST : Start bit P : Parity bit SP : Stop bit ST : Start bit P : Parity bit SP : Stop bit CLKi TxDi RxDi D0 D1 D2 D3 D4 D5 D6 D7 P SP ST SP ST P (1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first) P SP ST SP ST P (2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first) CLKi TxDi RxDi NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (no inverse). D0 D1 D2 D3 D4 D5 D6 D7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" 17.2.2 Selecting LSB First or MSB First As shown in Figure 17.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format. This function is available for 8-bit transfer data. Figure 17.16 Transfer Format 17.2.3 Serial Data Logic Inverse When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.17 shows a switching example of the serial data logic. Figure 17.17 Serial Data Logic Inverse |
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