Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

Preview PDF HTML

M32C/86 Datasheet(PDF) 230 Page - Renesas Technology Corp

Part # M32C/86
Description  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

M32C/86 Datasheet(HTML) 230 Page - Renesas Technology Corp

Back Button M32C/86 Datasheet HTML 226Page - Renesas Technology Corp M32C/86 Datasheet HTML 227Page - Renesas Technology Corp M32C/86 Datasheet HTML 228Page - Renesas Technology Corp M32C/86 Datasheet HTML 229Page - Renesas Technology Corp M32C/86 Datasheet HTML 230Page - Renesas Technology Corp M32C/86 Datasheet HTML 231Page - Renesas Technology Corp M32C/86 Datasheet HTML 232Page - Renesas Technology Corp M32C/86 Datasheet HTML 233Page - Renesas Technology Corp M32C/86 Datasheet HTML 234Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 230 / 505 page
background image
Page 207
9
7
4
f
o
5
0
0
2
,
8
0
.
p
e
S
0
0
.
1
.
v
e
R
0
0
1
0
-
4
0
2
0
B
9
0
J
E
R
17. Serial I/O (Special Function)
)
T
6
8
/
C
2
3
M
,
6
8
/
C
2
3
M
(
p
u
o
r
G
6
8
/
C
2
3
M
I/O
Timer
Delay Circuit
UARTi
Receive Register
External Clock
Arbitration
Detects Start Condition
Detects Stop Condition
Falling edge
detect
UARTi Transmission
NACK Interrupt
Request
UARTi Reception
ACK Interrupt Request
DMA Request
9th Pulse
Port reading
* When the IICM bit is set to "1", port pin can be read
regardless of the direction register being set to "1".
i=0 to 4
NOTES:
1. Set the PSj (j=0,1,3), PSLj or PSC register to determine.
IICM : Bit in the UiSMR register
IICM2 : Bit in the UiSMR2 register
LSYN bit
Bus Conflict
Start Condition Detect
Stop Condition Detect
Interrupt Request
Bus Conflict
Detect
I/O
Noise
Filter
SDAi
SCLi
CLK
Control
Internal Clock
UARTi
UARTi
I/O
Timer
CLKi
Data Register
D
T
Q
D
T
Q
D
T
Q
NACK
ACK
UARTi
UARTi
R
IICM
0
IICM=1 and
IICM2=0
0
IICM
IICM=1
IICM=0
S
R
Q
Bus
busy
1
IICM
ALS
R
S
SWC
Falling Edge of 9th Pulse
IICM=1 and
IICM2=0
IICM=0 or IICM2=1
IICM=0 or
IICM2=1
SWC2
SDHI
To DMA
To DMA
Transmit Register
UARTi
(Note1)
(Note 1)
1
1
Noise
Filter
Noise
Filter
IICM
0
1
0
(Note 1)
Q
Figure 17.19 I2C Mode Block Diagram



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com