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M32C/86 Datasheet(PDF) 228 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 228 Page - Renesas Technology Corp |
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228 / 505 page ![]() Page 205 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 17. Serial I/O (UART) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M P SP ST SP ST P P SP ST SP ST P TxDi (no inverse) Transfer Clock (1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse) RxDi (no inverse) TxDi (inverse) Transfer Clock (2) When the IOPOL bit in the UiMR register is set to "1" ( inverse) RxDi (inverse) NOTES: 1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). ST : Start bit P : Even parity SP : Stop bit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" 17.2.4 TxD and RxD I/O Polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity bit, are inversed. Figure 17.18 shows TxD and RxD I/O polarity inverse. Figure 17.18 TxD and RxD I/O Polarity Inverse |
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