M32CSLASH86 datasheet(241/505 Pages) RENESAS

241 / 505 page

Page 218

17. Serial I/O (Special Function)

)

(

Table 17.21 Pin Settings in Special Mode 2 (1)

Port

Function

Setting

PS0 Register

PSL0 Register

PD6 Register

P60

______

SS0 input

PS0_0=0

–

PD6_0=0

P61

CLK0 input (slave)

PS0_1=0

–

PD6_1=0

CLK0 output (master) PS0_1=1

––

P62

RxD0 input (master)

PS0_2=0

–

PD6_2=0

STxD0 output (slave)

PS0_2=1

PSL0_2=1

–

P63

TxD0 output (master)

PS0_3=1

––

SRxD0 input (slave)

PS0_3=0

–

PD6_3=0

P64

______

SS1 input

PS0_4=0

–

PD6_4=0

P65

CLK1 input (slave)

PS0_5=0

–

PD6_5=0

CLK1 output (master) PS0_5=1

––

P66

RxD1 input (master)

PS0_6=0

–

PD6_6=0

STxD1 output (slave)

PS0_6=1

PSL0_6=1

–

P67

TxD1 output (master)

PS0_7=1

––

SRxD1 input (slave)

PS0_7=0

–

PD6_7=0

Table 17.22 Pin Settings (2)

Port

Function

Setting

PS1 Register

PSL1 Register

PSC Register

PD7 Register

P70(1)

TxD2 output (master)

PS1_0=1

PSL1_0=0

PSC_0=0

–

SRxD2 input (slave)

PS1_0=0

––

PD7_0=0

P71(1)

RxD2 input (master)

PS1_1=0

––

PD7_1=0

STxD2 output (slave)

PS1_1=1

PSL1_1=1

PSC_1=0

–

P72

CLK2 input (slave)

PS1_2=0

––

PD7_2=0

CLK2 output (master)

PS1_2=1

PSL1_2=0

PSC_2=0

–

P73

______

SS2 input

PS1_3=0

–

PD7_3=0

NOTES:

1. P70 and P71 are ports for the N-channel open drain output.

Table 17.23 Pin Settings (3)

Port

Function

Setting

PS3 Register(1)

PSL3 Register

PSC3 Register

PD9 Register(1)

P90

CLK3 input (slave)

PS3_0=0

––

PD9_0=0

CLK3 output (master)

PS3_0=1

–––

P91

RxD3 input (master)

PS3_1=0

––

PD9_1=0

STxD3 output (slave)

PS3_1=1

PSL3_1=1

––

P92

TxD3 output (master)

PS3_2=1

PSL3_2=0

––

SRxD3 input (slave)

PS3_2=0

––

PD9_2=0

P93

______

SS3 input

PS3_3=0

PSL3_3=0

–

PD9_3=0

P94

_______

SS4 input

PS3_4=0

PSL3_4=0

–

PD9_4=0

P95

CLK4 input (slave)

PS3_5=0

PSL3_5=0

–

PD9_5=0

CLK4 output (master)

PS3_5=1

–––

P96

TxD4 output (master)

PS3_6=1

–

PSC3_6=0

–

SRxD4 input (slave)

PS3_6=0

PSL3_6=0

–

PD9_6=0

P97

RxD4 input (master)

PS3_7=0

––

PD9_7=0

STxD4 output (slave)

PS3_7=1

PSL3_7=1

––

NOTES:

1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not

generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set

the PD9 and PS3 registers.

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