M32CSLASH86 datasheet(242/505 Pages) RENESAS

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Page 219

17. Serial I/O (Special Function)

)

(

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17.4.1 SSi Input Pin Function (i=0 to 4)

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When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the special mode 2 is

selected, activating the pin function.

The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave.

______

When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting deter-

mines which master microcomputer is active and when.

17.4.1.1 When Setting the DINC Bit to "1" (Slave Mode)

_____

When a high-level ("H") signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a high-

impedance state and the transfer clock applied to the CLKi pin is ignored. When a low-level ("L") signal

_____

is applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled.

17.4.1.2 When Setting the DINC Bit to "0" (Master Mode)

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When using the SSi pin functin in master mode, set the UiIRS bit in the UiC1 register to "1" (transmis-

sion completed).

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When an "H" signal is applied to the SSi pin, serial communication is available due to transmission

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privilege. The master provides the transfer clock output. When an "L" signal is applied to the SSi pin,

it indicates that another master is active. The TxDi and CLKi pins are placed in high-impedance states

and the ERR bit in the UiSMR3 register is set to "1" (fault error) Use the transmit complete interrupt

routine to verify the ERR bit state.

To resume the serial communication after the fault error occurs, set the ERR bit to "0" while applying

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the "H" signal to the SSi pin. The TxDi and CLKi pins become ready for signal outputs.

P13

P12

Microcomputer

P93(SS3)

P92(TxD3)

P90(CLK3)

P91(RxD3)

P93(SS3)

P92(SRxD3)

P90(CLK3)

P91(STxD3)

P93(SS3)

P92(SRxD3)

P90(CLK3)

P91(STxD3)

Master

Slave

Microcomputer

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Figure 17.23 Serial Bus Communication Control with SS Pin

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