M32CSLASH86 datasheet(243/505 Pages) RENESAS

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17. Serial I/O (Special Function)

)

(

17.4.2 Clock Phase Setting Function

The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four

combinations of transfer clock polarity and phases.

The transfer clock phase and polarity must be the same between the master and the slave involved in the

transfer.

17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))

Figure 17.24 shows transmit and receive timing.

17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))

_____

When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin

_____

is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a

serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the

transfer clock. Figure 17.25 shows the transmit and receive timing.

_____

When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed

_____

in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis-

sion is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing.

Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock)

Signal Applied to

the SS Pin

Data Output Timing

Data Input Timing

"H"

"L"

Clock Output

(CKPOL=0, CKPH=0)

"H"

"L"

Clock Output

(CKPOL=1, CKPH=0)

"H"

"L"

Clock Output

(CKPOL=0, CKPH=1)

"H"

"L"

Clock Output

(CKPOL=1, CKPH=1)

"H"

"L"

"H"

"L"

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