ADE5166 datasheet(40/148 Pages) AD

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ADE5166/ADE5169

Rev. 0 | Page 40 of 148

Table 36. Accumulation Mode Register (ACCMODE, Address 0x0F)

Bit

Mnemonic

Default

Description

ICHANNEL

This bit indicates the current channel used to measure energy in antitampering mode.

0 = Channel A (IPA).

1 = Channel B (IPB).

FAULTSIGN

Configuration bit to select the event that triggers a fault interrupt.

0 = a FAULTSIGN interrupt occurs when the part enters fault mode.

1 = a FAULTSIGN interrupt occurs when the part enters normal mode.

VARSIGN1

Configuration bit to select the event that triggers a reactive power sign interrupt. If cleared to 0,

a VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1,

a VARSIGN interrupt occurs when reactive power changes from negative to positive.

APSIGN

Configuration bit to select event that triggers an active power sign interrupt. If cleared to 0,

an APSIGN interrupt occurs when active power changes from positive to negative. If set to 1,

an APSIGN interrupt occurs when active power changes from negative to positive.

ABSVARM1

Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.

SAVARM1

Logic 1 enables reactive power accumulation depending on the sign of the active power. If

active power is positive, var is accumulated as it is. If active power is negative, the sign of the var

is reversed for the accumulation. This accumulation mode affects both the var registers (VARHR,

RVARHR, LVARHR) and the pulse output when connected to VAR.1

POAM

Logic 1 enables positive-only accumulation of active power in energy register and pulse output.

ABSAM

Logic 1 enables absolute value accumulation of active power in energy register and pulse output.

1 This function is not available in the ADE5166.

Table 37. Gain Register (GAIN, Address 0x1B)

Bit

Mnemonic

Default

Description

[7:5]

PGA2

000

These bits define the voltage channel input gain.

PGA2

Result

000

Gain = 1

001

Gain = 2

010

Gain = 4

011

Gain = 8

100

Gain = 16

Reserved

Reserved.

CFSIGN_OPT

This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.

CFSIGN_OPT

Result

Filtered power signal

On a per CF pulse basis

[2:0]

PGA1

000

These bits define the current channel input gain.

PGA1

Result

000

Gain = 1

001

Gain = 2

010

Gain = 4

011

Gain = 8

100

Gain = 16

Table 38. Mode 3 Register (MODE3 Address 0x2B)

Bit

Mnemonic

Default

Description

[7:2]

Reserved

Reserved.

ZX1

Setting this bit enables the zero crossing output signal on P1.2.

ZX2

Setting this bit enables the zero crossing output signal on P0.5.

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