 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADE5166 Datasheet(PDF) 74 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADE5166 Datasheet(HTML) 74 Page - Analog Devices |
|
|
74 / 148 page  ADE5166/ADE5169 Rev. 0 | Page 74 of 148 Table 58. Program Control SFR (PCON, Address 0x87) Bit Mnemonic Default Description 7 SMOD 0 Double baud rate control. [6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation. Table 59. Data Pointer Low SFR (DPL, Address 0x82) Bit Mnemonic Default Description [7:0] DPL 0 These bits contain the low byte of the data pointer. Table 60. Data Pointer High SFR (DPH, Address 0x83) Bit Mnemonic Default Description [7:0] DPH 0 These bits contain the high byte of the data pointer. Table 61. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83) Bit Mnemonic Default Description [15:0] DP 0 These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs. Table 62. Stack Pointer SFR (SP, Address 0x81) Bit Mnemonic Default Description [7:0] SP 0 These bits contain the eight LSBs of the pointer for the stack. Table 63. Stack Pointer High SFR (SPH, Address 0xB7) Bit Mnemonic Default Description 7 Reserved 1 Reserved. This bit must be set to 1 for proper operation. 6 SBFLG 0 Stack bottom flag. 5 SSA[10] 0 Stack Starting Address Bit 10. 4 SSA[9] 0 Stack Starting Address Bit 9. 3 SSA[8] 1 Stack Starting Address Bit 8. 2 SP[10] 0 Stack Address Bit 10. 1 SP[9] 0 Stack Address Bit 9. 0 SP[8] 1 Stack Address Bit 8. Table 64. Stack Boundary SFR (STCON, Address 0xBF) Bit Mnemonic Default Description [7:3] WTRLINE 0 Contains the stack waterline setting bits. 2 INT_RST 0 Interrupt/reset selection bit. INT_RST Result 0 An interrupt is issued when a stack violation occurs 1 A reset is issued when a stack violation occurs 1 SBE 0 Stack boundary enable bit. 0 WTRLFG 0 Waterline flag. Table 65. Configuration SFR (CFG, Address 0xAF) Bit Mnemonic Default Description 7 Reserved 1 Reserved. This bit should be left set for proper operation. 6 EXTEN 0 Enhanced UART enable bit. EXTEN Result 0 Standard 8052 UART without enhanced error checking features 1 Enhanced UART with enhanced error checking (see the UART Additional Features section) 5 SCPS 0 Synchronous communication selection bit. SCPS Result 0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs 1 SPI port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
