MPC5200BDS datasheet(46/72 Pages) FREESCALE

46 / 72 page

MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

NOTE

Output timing is specified at a nominal 50 pF load.

Figure 36. Timing Diagram—I2C Input/Output

1.3.15

J1850

See the MPC5200B User Manual.

Table 41. I2C Output Timing Specifications—SCL and SDA

Sym

Description

Min

Max

Units

SpecID

1(1)

1 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The

I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed in IFDR.

Start condition hold time

—

IP-Bus Cycle(3)

A13.8

2(1)

Clock low time

—

IP-Bus Cycle(3)

A13.9

3(2)

2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL

or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values

SCL/SDA rise time

—

7.9

A13.10

4(1)

Data hold time

—

IP-Bus Cycle(3) A13.11

5(1)

SCL/SDA fall time

—

7.9

A13.12

6(1)

Clock high time

—

IP-Bus Cycle(3) A13.13

7(1)

Data setup time

—

IP-Bus Cycle(3) A13.14

8(1)

Start condition setup time (for repeated start condition

only)

—

IP-Bus Cycle(3) A13.15

9(1)

Stop condition setup time

—

IP-Bus Cycle(3)

3 Inter Peripheral Clock is defined in the MPC5200B User Manual.

A13.16

SCL

SDA

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