MPC5200BDS datasheet(19/72 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 3

Freescale Semiconductor

Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing

1.3.6.3

Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value

is calculated automatically by hardware.

Table 20. DDR SDRAM Memory Read Timing

Sym

Description

Min

Max

Units

SpecID

tmem_clk

MEM_CLK period

7.5

—

A5.15

tvalid

Control Signals, Address and MBA

valid after rising edge of MEM_CLK

—tmem_clk*0.5+0.4

A5.16

thold

Control Signals, Address and MBA

hold after rising edge of MEM_CLK

tmem_clk*0.5

—

A5.17

datasetup

Setup time relative to MDQS

—

0.4

A5.18

datahold

Hold time relative to MDQS

2.6

—

A5.19

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Active

NOP

WRITE

NOP

thold

Row

Column

MBA (Bank Selects)

datahold

datavalid

tvalid

thold

tvalid

thold

tvalid

DQM (Data Mask)

DMvalid

DMhold

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