ML2724_05 datasheet(10/26 Pages) MICRO-LINEAR

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ML2724

DS2724-F-03

FINAL DATASHEET

DECEMBER 2005 10

MODE CONTROL AND INTERFACE LINES

XCEN

I (CMOS)

Enables the bandgap reference and

voltage regulators when high. Consumes

only leakage current in STANDBY mode

when low. This is a CMOS input, and the

thresholds are referenced to VDD and

VSS.

RXON

I (CMOS)

TX/RX Control Input. Switches the

transceiver between TRANSMIT and

RECEIVE modes. Circuits are powered

up and signal paths reconfigured

according to the operating mode. This is

a CMOS input, and the thresholds are

referenced to VDD and VSS.

VSS

XCEN

VDD

RXON

DIN

PAON

O (CMOS)

PA Control Output. Enables the off-chip

PA at the correct times in a Transmit slot.

Goes high when transmit RF is present

at TXO; goes low

5μs before transmit RF

is removed from TXO. Has interlock logic

to shut down the PA if the PLL does not

lock.

VSS

VDD

PAON

FREF

Input for the 12.288MHz or 6.144MHz

reference frequency. This input is used

as the reference frequency for the PLL

and as a calibration frequency for the on-

chip filters. An AC-coupled sine or

square wave source drives this self-

biased input.

VSS

FREF

VCCA

40k

QPO

Charge Pump Output of the phase

detector. This is connected to the

external PLL loop filter.

VSS

RVPLL

11 QPO

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