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F75111RG Datasheet(PDF) 22 Page - Feature Integration Technology Inc.

Part # F75111RG
Description  Low Power GPIO Datasheet
PDF  45 Pages
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Manufacturer  FINTEK [Feature Integration Technology Inc.]
Direct Link  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F75111RG Datasheet(HTML) 22 Page - Feature Integration Technology Inc.

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July, 2007
V0.27P
- 20 -
F75111
input mode [CR10] will enable GPIO17 edge detection. Default is
disable
6
EN_GP16EDGE
R/W
VSB3V
Enable GPIO16 Edge Detector. If this bit set to 1 and GPIO16 set to
input mode [CR10] will enable GPIO16 edge detection. Default is
disable
5
EN_GP15EDGE
R/W
VSB3V
Enable GPIO15 Edge Detector. If this bit set to 1 and GPIO15 set to
input mode [CR10] will enable GPIO15 edge detection. Default is
disable
4
EN_GP14EDGE
R/W
VSB3V
Enable GPIO14 Edge Detector. If this bit set to 1 and GPIO14 set to
input mode [CR10] will enable GPIO14 edge detection. Default is
disable
3
EN_GP13EDGE
R/W
VSB3V
Enable GPIO13 Edge Detector. If this bit set to 1 and GPIO13 set to
input mode [CR10] will enable GPIO13 edge detection. Default is
disable
2
EN_GP12EDGE
R/W
VSB3V
Enable GPIO12 Edge Detector. If this bit set to 1 and GPIO12 set to
input mode [CR10] will enable GPIO12 edge detection. Default is
disable. If this bit serves as IRQ/SMI#, this bit has no effect.
1
EN_GP11EDGE
R/W
VSB3V
Enable GPIO11 Edge Detector. If this bit set to 1 and GPIO11 set to
input mode [CR10] will enable GPIO11 edge detection. Default is
disable
0
EN_GP10EDGE
R/W
VSB3V
Enable GPIO10 Edge Detector. If this bit set to 1 and GPIO10 set to
input mode [CR10] will enable GPIO10 edge detection. Default is
disable
7.19 GP1X Edge Detector Status Register – Index 0x19
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
STS_GP17ED
GE
RW
VSB3V
Indicate GPIO17 Edge Status. If set to 1, the edge of GPIO17 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
6
STS_GP16ED
GE
RW
VSB3V
Indicate GPIO16 Edge Status. If set to 1, the edge of GPIO16 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
5
STS_GP15ED
GE
RW
VSB3V
Indicate GPIO15 Edge Status. If set to 1, the edge of GPIO15 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.
4
STS_GP14ED
GE
RW
VSB3V
Indicate GPIO14 Edge Status. If set to 1, the edge of GPIO14 has
occurred. Writing 1 will clear this bit to 0. Writing 0 is invalid.



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