LTC1646IGN datasheet(6/20 Pages) LINER

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LTC1646

1646fa

PWRGD (Pin 4) :Open Drain Power Good Digital Output.

Connect the CPCI HEALTHY# signal to the PWRGD pin.

PWRGD remains low while V3VOUT ≥ 2.9V and V5VOUT ≥

4.65V. When either of the supplies falls below its power

good threshold voltage, PWRGD will go high after a 50

µs

deglitching time.

5VOUT (Pin 5): 5V Output Sense. The PWRGD pin will not

pull low until the 5VOUT pin voltage exceeds 4.65V. If no 5V

input supply is available, tie the 5VOUT pin to the 3VOUT pin

in order to disable the 5VOUT power good function.

GND (Pin 6): Chip Ground

3VOUT (Pin 7): 3.3V Output Sense. The PWRGD pin will not

pull low until the 3VOUT pin voltage exceeds 2.90V. If no

3.3V input supply is available, tie the 3VOUT pin to the

5VOUT pin.

3VIN (Pin 8): 3.3V Supply Sense Input. An undervoltage

lockout circuit prevents the switches from turning on

when the voltage at the 3VIN pin is less than 2.5V. If no 3.3V

input supply is available, connect a diode between 5VIN

and 3VIN (tie anode to 5VIN and cathode to 3VIN ). See

Figure 11.

RESETOUT (Pin 1): Open Drain Digital Output. Connect

the CPCI LOCAL_PCI_RST# signal to the RESETOUT pin.

RESETOUT is the logical combination of RESETIN and

PWRGD (see Table 4).

TIMER (Pin 2): Current Fault Inhibit Timing Input. Connect

a capacitor from TIMER to GND. With the chip turned off,

the TIMER pin is internally held at GND. When the chip is

turned on, a 5

µA pull-up current source is connected to

TIMER. Current limit and voltage compliance faults will be

ignored until the voltage at the TIMER pin is greater than

1.25V.

FAULT (Pin 3): Open Drain Digital I/O. FAULT is pulled low

when a current limit fault is detected. Faults are ignored

while the voltage at the TIMER pin is less than 1.25V. Once

the TIMER cycle is complete, FAULT will pull low and the

chip will latch off in the event of an overcurrent fault. The

chip will remain latched in the off state until the OFF/ON pin

is cycled high then low or the power is cycled.

Forcing the FAULT pin low with an external pull-down will

cause the chip to be latched into the off state after a 21

µs

deglitching time.

TYPICAL PERFOR A CE CHARACTERISTICS

RESETOUT, PWRGD and FAULT

Output Low Voltage vs ISINK

5VOUT/3VOUT Discharge

Impedance vs Temperature

–50

–25

100

TEMPERATURE (

°C)

1646 G23

180

160

140

120

100

ISINK (mA)

1646 G22

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

°C

–45

°C

PI FU CTIO S

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