STA2500D datasheet(14/57 Pages) STMICROELECTRONICS

14 / 57 page

Pinout

STA2500D

14/57

Doc ID 16067 Rev 1

For the output pin the default drive capability is 2 mA, except for pin K3 (BT_GPIO_11) and

pin L3 (BT_GPIO_8) where it is 8 mA such that when used for Class 1, these 2 pins can be

used for a switch control in a cheaper way.

Table 13.

The STA2500D pin list (functional and supply)

Name

Description

Type

Reset(1)

Default(2)

after reset

Clock and reset pins

BT_RESETN

Global reset - active low

BT_REF_CLK_IN

Reference clock input(3)

Input

BT_LP_CLK

Low power clock input

SW initiated low power mode

BT_CLK_REQ_OUT_1 C4

Wake-up signal to Host (Active high or Active

low, depending on configuration pins)

I/O(4)

Input PD/PU,

depends on

config

Output

depends on

config

BT_CLK_REQ_OUT_2 G7

Wake-up signal to Host. Active low

(SPI mode only)

Input PU

I/O depends

on config

BT_CLK_REQ_IN_1

Clock request input (Active high)

Input PD

BT_CLK_REQ_IN_2

Clock request input (Active low)

Input PU

BT_HOST_WAKEUP/

BT_SPI_INT

Wake-up signal to Host or SPI interrupt

Input PD

Output

BT_WAKEUP

Wake-up signal to Bluetooth (Active high)

I/O

Input (5)

Input

UART interface

BT_UART_RXD/

BT_SPI_DI

UART receive data

I/O(4)

Input PD

SPI data in

Input PD

BT_UART_TXD/

BT_SPI_DO

UART transmit data

Output high

SPI data out

Input PD

BT_UART_CTS/

BT_SPI_CLK

UART clear to send

Input PU

SPI clock

Input PD

BT_UART_RTS/

BT_SPI_CSN

UART request to send

Output low

SPI chip select

Input PU

PCM interface

BT_PCM_SYNC

PCM frame signal

I/O(4) Input PD

Input PD

BT_PCM_CLK

PCM clock signal

BT_PCM_A

PCM data

BT_PCM_B

PCM data

JTAG interface

BT_GPIO_9

JTAG_TDI or GPIO

Input PU(6)

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