STA2500D datasheet(43/57 Pages) STMICROELECTRONICS

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STA2500D

Digital interfaces

Doc ID 16067 Rev 1

43/57

Figure 18.

SPI setup and hold timing

7.3

The PCM interface

The chip contains a 4-pin direct voice interface to connect to standard CODEC.

The interface supports multiport PCM operations for voice transfer. It can be programmed to

act as a Master or a Slave via a SW parameter download or via specific HCI commands.

The four signals of the multi-port PCM interface are:

●

PCM_CLK

: PCM clock

●

PCM_SYNC : PCM 8 kHz sync (every 125

μs)

●

PCM_A

: PCM data (TX or RX)

●

PCM_B

: PCM data (RX or TX)

As a Master the interface by default generates a PCM clock rate of 2048 kHz, but it can be

configured to rates from 8 kHz up to 2048 kHz. As a Slave, it can automatically handle

external PCM clock rates from 128 kHz up to 4000 kHz. The default PCM_SYNC rate is 8

kHz.

The following external PCM data format are supported: linear (13 - 16 bit), µ

−law (8 bit) or A-

law (8 bit).

Table 26.

SPI timing parameters

Symbol

Description

Min.

Typ.

Max.

Unit

PCL

SPI_CLK full period

TCLH

High period of SPI_CLK

16.6

TCLL

Low period of SPI_CLK

26.4

TCSH

High period of SPI_CSN

1 * PCL

TCSL

Low period of SPI_CSN

9 * PCL

TSCS

Setup time, SPI_CSN Low to SPI_CLK high

1 * PCL

TSCL

Setup time, SPI_CLK Low to SPI_CSN high

2 * PCL

TSDC

Setup time, SPI_MOSI valid to SPI_CLK high

9.7

THCD

Hold time, SPI_MOSI valid after SPI_CLK

high

0ns

TSCLD

Setup time, SPI_CLK Low to SPI_MISO valid

26.5

SP I_CS N

SPI_C LK

SP I_DI

SP I_DO

TCSL

TCSH

TSCL

TCLL

TCLH

TSCS

P CL

TSCLD

TSDC

THCD

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