WM8170 datasheet(24/41 Pages) WOLFSON

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WM8170

Product Preview Rev 1.0

WOLFSON MICROELECTRONICS LTD

PP Rev 1.0 March 2000

BLCENB CONTROLLED PULSE GENERATOR

The internal master clock derived from the SHP and SHD digital inputs clocks the INTBLCENB pulse

generator. The pulse generator is controlled by the BLCENB input, and is used to generate an

internal pulse that is timed relative to the falling edge of the BLCENB input. This pulse can be

selectively used to control either the analogue control loop or the IIR filter. The Pulse Steering Circuit

is reset by a falling edge on the VD input so that the user can determine which video lines will enable

the Analogue Correction Circuitry and which will enable the IIR Filter.

Enabling the analogue DC correction circuitry is required to remove the majority of the offset from the

incoming video. The value of this offset at the input to the ADC is dependent on the gain of the PGA,

hence the analogue DC correction circuitry should be enabled either at the beginning of each frame,

or only when the PGA gain is changed.

Figure 19 shows the generation of the INTBLCENB pulse relative to the falling edge of the BLCENB

pin. There are two Management Interface registers that control the generation of the INTBLCENB

signal. CLPDEL[7:0] defines the delay in pixel periods from the falling edge of BLCENB pin to the

falling edge of the INTBLCENB signal. The delay is equal to CLPDEL+1 pixels. CLPWID[7:0] defines

the width of the INTBLCENB signal. The width of the signal is CLPWID pixels.

MCLK (Internal)

BLCENB

SHD

SHP

INTBLCENB

CLPDEL+1 PIXELS

CLPWID PIXELS

EDGE WHICH

SAMPLES BLCENB

Figure 19 Generating the INTBLCENB Pulse

STEERING THE INTBLCENB SIGNAL

Figure 20 shows how the INTBLCENB signal can be steered to either the Analogue Loop Enable, or

to the IIR Filter Enable. There are two Management Interface Registers which control how the

INTBLCENB signal is steered. ANDEL[7:0] defines the delay in INTBLCENB pulses from the falling

edge of the VD input. The INTBLCENB pulses during this period are steered to the IIR Filter. The

delay is equal to ANDEL. ANLINE[7:0] is defines the number of INTBLCENB pulses steered to the

Analogue Loop Enable. The number is equal to ANLINE. The INTBLCENB pulse is steered to the IIR

Filter whenever it is not used for the Analogue Loop Enable.

BLCENB

INTBLCENB

ANALOGUE

ENABLE

IIR FILTER

ENABLE

PROGRAMMABLE DELAY IN

INTBLCENB PULSES = ANDEL

PROGRAMMABLE NUMBER OF

INTBLCENB PULSES = ANLINE

INTBLCENB GENERATED RELATIVE TO

FALLING EDGE OF BLCENB

Figure 20 Steering the INTBLCENB Signal

The steering circuitry allows the user to select which lines of the input video the analogue DC

correction loop will be enabled for, and to place these lines in a non viewed section of the frame. The

lines which have the analogue DC correction loop enabled will be subject to line noise due to the

correction value that is being applied only having been calculated over only a small number of pixels.

The effect of line noise during the analogue loop enables can be minimized if a large number of

pixels are used to calculate the digital average. This can be achieved if the analogue loop is enabled

during the optically black lines at the beginning of a video frame.

WM8170 Datasheet(PDF) 24 Page - Wolfson Microelectronics plc

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