PCF2123_09 datasheet(5/55 Pages) NXP

5 / 55 page

PCF2123_2

Product data sheet

Rev. 02 — 4 December 2009

5 of 55

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

7.2 Pin description

[1]

The die paddle (exposed pad) is wired to VSS but should not be electrically contacted.

[2]

The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.

Device protection diagram

Table 3.

Pin description

Symbol

Description

TSSOP14

HVQFN16

PCF2123Ux

OSCI

oscillator input; high-impedance node; minimize wire length

between quartz and package

OSCO

oscillator output; high-impedance node; minimize wire

length between quartz and package

n.c.

3, 11

6, 7, 14, 15

do not connect and do not use as feed through; connect to

VDD if ﬂoating pins are not allowed

TEST

test pin; not user accessible; connect to VSS or leave

ﬂoating (internally pulled down)

INT

interrupt output (open-drain; active LOW)

chip enable input (active HIGH) with internal pull down

VSS

75[1]

12[2]

ground

SDO

serial data output, push-pull; high-impedance when not

driving; can be connected to SDI for single wire data line

SDI

serial data input; may ﬂoat when CE is inactive

SCL

serial clock input; may ﬂoat when CE is inactive

CLKOE

CLKOUT enable or disable pin; enable is active HIGH

CLKOUT

clock output (open-drain)

VDD

supply voltage; positive or negative steps in VDD may affect

oscillator performance; recommend 100 nF decoupling

close to device (see Figure 29)

Fig 5.

Device diode protection diagram of PCF2123

001aai552

SDO

SDI

SCL

CLKOUT

CLKOE

VDD

OSCI

OSCO

TEST

INT

VSS

PCF2123

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