ATSAM3U datasheet(27/62 Pages) ATMEL

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6430CS–ATARM–09-Apr-10

SAM3U Series

7.4

Matrix Slaves

The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a dif-

ferent arbitration per slave.

7.5

Master to Slave Access

All the Masters can normally access all the Slaves. However, some paths do not make sense,

for example allowing access from the USB Device High speed DMA to the Internal Peripherals.

Thus, these paths are forbidden or simply not wired, and shown as “–” in Table 7-3 below.

Table 7-2.

List of Bus Matrix Slaves

Slave 0

Internal SRAM0

Slave 1

Internal SRAM1

Slave 2

Internal ROM

Slave 3

Internal Flash 0

Slave 4

Internal Flash 1

Slave 5

USB Device High Speed Dual Port RAM (DPR)

Slave 6

NAND Flash Controller RAM

Slave 7

External Bus Interface

Slave 8

Low Speed Peripheral Bridge

Slave 9

High Speed Peripheral Bridge

Table 7-3.

SAM3U Master to Slave Access

Slaves

Masters

234

Cortex-M3

I/D Bus

Cortex-M3 S

Bus

PDC

USB Device

High Speed

DMA

Controller

Internal SRAM0

–

XXXX

Internal SRAM1

–

XXXX

Internal ROM

–

Internal Flash 0

––––

Internal Flash 1

––––

USB Device High Speed Dual Port RAM (DPR)

–

NAND Flash Controller RAM

–

XXXX

External Bus Interface

–

XXXX

Low Speed Peripheral Bridge

–

High Speed Peripheral Bridge

–

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