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ATSAM3U Datasheet(PDF) 29 Page - ATMEL Corporation |
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ATSAM3U Datasheet(HTML) 29 Page - ATMEL Corporation |
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29 / 62 page ![]() 29 6430CS–ATARM–09-Apr-10 SAM3U Series The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): 7.8 Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. • Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access • Flash Patch and Breakpoint (FPB) unit for implementing break points and code patches • Data Watchpoint and Trace (DWT) unit for implementing watch points, data tracing, and system profiling • Instrumentation Trace Macrocell (ITM) for support of printf style debugging •IEEE® 1149.1 JTAG Boundary-scan on all digital pins Table 7-5. Peripheral DMA Controller Instance name Channel T/R TWI1 Transmit TWI0 Transmit PWM Transmit UART Transmit USART3 Transmit USART2 Transmit USART1 Transmit USART0 Transmit TWI0 Receive TWI1 Receive UART Receive USART3 Receive USART2 Receive USART1 Receive USART0 Receive ADC Receive ADC12B Receive |
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