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R5F10RF8AFP Datasheet(PDF) 48 Page - Renesas Technology Corp |
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R5F10RF8AFP Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 76 page  RL78/L12 2. ELECTRICAL SPECIFICATIONS (TARGET) Page 48 of 73 R01DS0157EJ0001 Rev.0.01 2012.02.20 Under development Preliminary document Specifications in this document are tentative and subject to change. Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin products. CSI mode connection diagram (during communication at different potential) Vb Rb User's device <Master> SCKp SOp SCK SI SIp SO Vb Rb RL78/L12 Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 2. Use it with EVDD ≥ Vb. Remarks 1. Rb[ Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM number (g = 1) 3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at different potentials in CSI mode. 4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V 2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V 1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V |
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