MPC5744P datasheet(3/114 Pages) FREESCALE

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Introduction

MPC5744P Data Sheet, Rev. 0.3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Introduction

1.1

Feature list

Table 1 summarizes major features of the MPC5744P device. The feature column represents a

combination of module names and capabilities of certain modules.

Table 1. MPC5744P feature summary

Feature

Details

CPU

Power Architecture

2 x e200z4 in delayed lock step

Architecture

Harvard

Execution Speed

0 MHz to TBD (design target: 180 MHz or greater) (+2% FM)

Embedded FPU

Yes

Core MPU

24 regions

Instruction Set PPC

Instruction Set VLE

Yes

Instruction cache

8 KB, EDC

Data cache

4 KB, EDC

Data local memory

64 KB, ECC

System MPU

Yes (16 regions)

Buses

Core bus

AHB, 32-bit address, 64-bit data, e2e ECC

Internal periphery bus

32-bit address, 32-bit data

Crossbar

Master x slave ports

4 x 5

Memory

Code/data flash memory

2.5 MB, ECC, RWW

Data flash memory

Supported with RWW

SRAM

384 KB, ECC

Modules

Interrupt controller

32 interrupt priority levels, 16 software programmable interrupts

PIT

1 module with 4 channels

System Timer Module (STM)

1 module with 4 channels

Software Watchdog Timer (SWT)

Yes

eDMA

32 channels, in delayed lock step

FlexRay

1 module with 64 message buffer, dual channel

MPC5744P Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

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