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TNETA1570 Datasheet(PDF) 14 Page - Texas Instruments

Part # TNETA1570
Description  ATM SEGMENTATION AND REASSEMBLY DEVICE WITH INTEGRATED 64-BIT PCI-HOST INTERFACE
PDF  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETA1570 Datasheet(HTML) 14 Page - Texas Instruments

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TNETA1570
ATM SEGMENTATION AND REASSEMBLY DEVICE
WITH INTEGRATED 64BIT PCIHOST INTERFACE
SDNS033B − JUNE 1995 − REVISED MAY 1996
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing requirements (see Figure 5)
NO.
MIN
MAX
UNIT
1
tsu(PGNT)
Setup time, PGNT low before PCLK
↑
10
ns
2
tsu(PTRDY)
Setup time, PTRDY low before PCLK
↑
7
ns
3
tsu(PDEVSEL)
Setup time, PDEVSEL low before PCLK
↑
7
ns
4
th(PTRDY)
Hold time, PTRDY low after PCLK
↑
2
ns
5
th(PDEVSEL)
Hold time, PDEVSEL low after PCLK
↑
2
ns
operating characteristics (see Figure 5)
NO.
MIN
MAX
UNIT
6
td(PREQ)
Delay time, PCLK
↑ to PREQ↓
2
12
ns
7
td(PFRAME)
Delay time, PCLK
↑ to PFRAME↓
2
11
ns
8
td(PCBE)
Delay time, PCLK
↑ to PCBE valid
2
11
ns
9
td(PIRDY)
Delay time, PCLK
↑ to PIRDY↓
2
11
ns
10
td(PAD)
Delay time, PCLK
↑ to PAD31−PAD0 valid
2
11
ns
11
td(PSB)
Delay time, PCLK
↑ to PSB1−PSB0 valid
2
11
ns
PCLK
(input)
PREQ
(output)
PGNT
(input)
PAD31 −
PAD 0
(output)
PFRAME
(output)
PCBE3 −
PCBE0
(output)
PIRDY
(output)
PTRDY
(input)
PDEVSEL
(input)
6
1
10
7
8
9
2
3
Address
Bus Command
Data 1
Data 2
Data 4
BE No. S-1
BE No. S-2
BE No. S-3
Data 3
BE No. S-4
4
5
Data Phase
Address Phase
11
PSB1−
PSB0
(output)
Figure 5. TNETA1570 Write Operation (PCI SAR as Master)



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