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TNETA1575 Datasheet(PDF) 31 Page - Texas Instruments |
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TNETA1575 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 45 page ![]() TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 31 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics (see Figure 13) control-memory interface (write operation) data bus enable and disable times NO. PARAMETER MIN MAX UNIT 1 ten(PH-CE) Enable time, from PCLK ↑ to CMDATA31–CMDATA0 enabled 5 10 ns 2 tdis(PH-CZ) Disable time, from PCLK ↑ to CMDATA31–CMDATA0 disabled (Z state) 6 11 ns CMAD15- CMAD0 (output) CMOE (output) CMWE (output) CMDATA31- CMDATA0 (output) 1 Valid Z PCLK (input) 2 Z Figure 13. Control-Memory Interface (Write Operation) – Data Bus Enable and Disable Times |
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