TNETA1575 datasheet(6/45 Pages) TI1

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TNETA1575

ATM SEGMENTATION AND REASSEMBLY DEVICE

WITH PCI-HOST AND COPROCESSOR INTERFACES

SDNS040C – MAY 1996 – REVISED JUNE 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

high-priority segmentation (request and acknowledge)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

HPSACK

108

(CMOS)

High-priority segmentation acknowledge. HPSACK is asserted for one PCI-bus clock cycle to

acknowledge that HPSREQ is detected.

HPSREQ

109

(TTL)

High-priority segmentation request. HPSREQ is sampled at each new segmentation opportunity

and is synchronous to the PCI-bus clock. When HPSREQ is active, TNETA1575 initiates the

procedure for transmitting a cell from TX DMA channel 1. To ensure that the high-priority

segmentation request is processed, HPSREQ remains active until HPSACK is set low. HPSREQ

is deasserted within two PCI-bus clock cycles of when HPSACK is asserted.

cell-reassembly interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Reassembly cell available

RESCLAV

(CMOS)

PHY mode

RESCLAV (TXFULL/TXCLAV) indicates that a transfer of a complete cell can be

accepted.

(CMOS)

ATM mode

RESCLAV (RXENB) indicates that a valid byte RESDATA will be sent during the next

clock cycle.

Reassembly clock

RESCLK

(TTL)

PHY mode

RESCLK (TXCLK) is used to synchronize transfers on RESDATA. The UTOPIA

interface is used as the source for RESCLK.

(TTL)

ATM mode

RESCLK (RXCLK) is used to synchronize transfers on RESDATA. ATMCLK is used

as the source for RESCLK.

RESDATA7

72 75

Reassembly data

RESDATA7–

RESDATA0

72–75,

77–80

(TTL)

PHY mode

RESDATA7–RESDATA0 (TXDATA). RESDATA7 is the most significant bit.

RESDATA0

77–80

(TTL)

ATM mode

RESDATA7–RESDATA0 (RXDATA). RESDATA7 is the most significant bit.

Reassembly enable

RESEN

PHY mode

RESEN (TXENB) goes active low when RESDATA contains a valid byte.

RESEN

(TTL)

ATM mode

RESEN (RXEMPTY/RXCLAV) indicates that transfer of a complete cell can be

accepted.

Reassembly parity

RESPAR

(TTL)

PHY mode

RESPAR (TXPAR) is the odd-parity bit over RESDATA7–RESDATA0.

(TTL)

ATM mode

RESPAR (RXPAR) is the odd-parity bit over RESDATA7–RESDATA0.

Reassembly parity error (not required by UTOPIA)

RESPERR

(CMOS)

PHY mode

RESPERR indicates that parity error was present at the previous rising edge of

(CMOS)

ATM mode

RESCLK.

Reassembly start of cell

RESSOC

(TTL)

PHY mode

RESSOC (TXSOC) is received when RESDATA contains the first valid byte of the

cell.

(TTL)

ATM mode

RESSOC (RXSOC) is received when RESDATA contains the first valid byte of the

cell.

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