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ST802RT1B Datasheet(PDF) 24 Page - STMicroelectronics |
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ST802RT1B Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 58 page  Registers and descriptors description ST802RT1A, ST802RT1B 24/58 Doc ID 17049 Rev 1 suppressed from transmission. Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. Even though bit 9 (advertise 100BASE-T4) is writable, it should never be set since the ST802RT1x does not support T4 operation. Advertised selector: Bits 4:0 of the advertisement register contain the fixed value “00001”, indicating that the chip belongs to the 802.3 class of PHY transceivers LP next page: Bit 15 of the link partner ability register returns a value of “1” when the link partner implements the next page function and has next page information that it wants to transmit. LP ack: Bit 14 of the link partner ability register is used by auto-negotiation to indicate that a device has successfully received its link partner's link code word. LP remote fault: Bit 13 of the link partner ability register returns a value of “1” when the link partner signals that a remote fault has occurred. The ST802RT1x simply copies the value to this register and does not act upon it. Table 15. RN05 [0d05, 0x05]: Auto-negotiation link partner ability register Bit Bit name Description Default RW type Type 15 LP Next Page 1 -> Link partner desires next page transfer 0 -> Link partner does not desire next page transfer 0RO - 14 LP Acknowledge 1 -> Link partner acknowledges reception of the ability data word 0 -> Acknowledge not yet received 0RO - 13 LP Remote Fault 1 -> Remote fault indicated by link partner 0 -> No remote fault indicated by link partner 0RO - 12 RESERVED -- 0 RO - 11 Asymmetric Pause (full- duplex) 1 -> LP supports asymmetric pause (MAC level: clause 31, annex 31B of 802.3u) 0 -> LP has no MAC-based full-duplex flow control. 0RO - 10 LP pause (full- duplex) 1 -> LP supports symmetric pause (MAC level: clause 31, annex 31B of 802.3u) 0 -> LP has no MAC-based full-duplex flow control. 0RO - 9 100BASE-T4 1 -> LP supports 100BASE-T4 0 -> LP does not support 100BASE-T4 0RO - 8 100BASE-TX full duplex 1 -> LP supports 100BASE-TX full-duplex 0 -> LP does not support 100BASE-TX full-duplex 0RO - 7 100BASE-TX 1 -> LP supports 100BASE-TX 0 -> LP does not support 100BASE-TX 0RO - 6 10BASE-T full duplex 1 -> LP supports 10BASE-T full-duplex 0 -> LP does not support 10BASE-T full-duplex 0RO - 5 10BASE-T 1 -> LP supports 10BASE-T 0 -> LP does not support 10BASE-T 0RO - 4:0 LP selector field LP's binary encoded protocol selector 00000b RO - |
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