AB-557-03 datasheet(1/7 Pages) ABRACON

Part #	AB-557-03

Description	CRYSTAL-LESS PCI EXPRESS DUAL OUTPUT ULTRA MINIATURE PURE SILICONTM SMD CLOCK GENERATOR

PDF	7 Pages

Scroll/Zoom	100%

Manufacturer	ABRACON [Abracon Corporation]

Direct Link	https://abracon.com

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1 / 7 page

AB-557-03 Series

APPLICATIONS:

FEATURES:

Pb RoHS

Compliant

CRYSTAL-LESS PCI EXPRESS DUAL OUTPUT ULTRA MINIATURE

PURE SILICONTMSMD CLOCK GENERATOR

STANDARD SPECIFICATIONS:

ABRACON IS

CERTIFIED

ABRACON IS

ISO9001:2008

CERTIFIED

30332 Esperanza, Rancho Santa Margarita, California 92688

tel 949-546-8000 | fax 949-546-8001| www.abracon.com

Revised: 10.31.12

Visit www.abracon.com for Terms & Conditions of Sale

3.2 x 2.5 x 0.85 mm (14 Pin QFN)

5.1 x 4.5 x 1.1 mm (16 Pin TSSOP)

Pb RoHS

Compliant

• Solid State Storage

• Storage Area Networks

• Passive Optical Networks

• Ethernet: 1G, 10GBASE-T/KR/LR/SR, and FCoE

• TV and other Consumer Electronics

• Industrial and Medical

• Scanner, Printer

• Meets PCIe Gen1, Gen2, & Gen3 specs.

• High Performance MEMS Technology by Discera

• Available Mixed Output Formats: HCSL, LVPECL, LVDS or LVCMOS

• Wide Temperature Range: -40° to 105° C

• Wide Supply Range: 2.25V to 3.6 V

• Low Power Consumption

• Excellent Shock & Vibration Immunity

*1. For frequency other than 100MHz, please contact ABRACON or consider using ASEMDxx series

2. Frequency stability includes frequency variations due to initial tolerance, temp. and power supply voltage

Parameters

Minimum

Typical

Maximum

Unite

Notes

Frequency

f0

2.3

100

460*1

MHz

Operating Temperature

-20

+70

°C

See options

C

°

0

5

1

+

5

-

e

r

u

t

a

r

e

p

m

e

T

e

g

a

r

o

t

S

Overall Freq. Stability*2

Δf

-50

+50

ppm

See options

Supply Voltage

VDD

+2.25

+3.6

V

Supply Current- Enabled

IDD

60

mA

RL=50Ω,

F01=F02=100.00MHz

Supply Current- Disabled

IDD

21

23

mA

Startup Time

tsu

5

ms

Enable Time

tEN

20

ns

Disable Time

tDA

5

ns

Tri-state Function (Standby/Disable)

"1" (VIH≥0.75*Vdd) or Open: Oscillation

"0" (VIL<0.25*Vdd) : Hi Z

V

40kΩ pull-up resistor

embedded

r

a

e

y

t

s

ri

F

m

p

0

.

5

+

0

.

5

-

g

n

i

g

A

VOH

0.725

Output Offset Voltage

VOL

0.10

V

RL=50 Ω

Peak to Peak Output Swing

750

mV

Single-Ended

Rise Time

tr

200

400

ps

Fall Time

tf

200

400

ps

RL=50 Ω, CL=2pF

(20% to 80%)*VDD

Duty Cycle

SYM

48

52

%

Differential

Period Jitter

JPER

2.5

psRMS F01=F02=100.00MHz

RJ

0.540

psRMS

DJ

0.832

41.9

TJ

8.536

86.0

psp-p

PCIe Gen 1.1

TJ= DJ + 14.069 x RJ

(BER 10-12)

JRMS-CCHF

0.458

3.1

PCIe Gen 2.1

1.5 MHz to Nyquist

JRMS-CCLF

0.030

3.0

psRMS

PCIe Gen 2.1

10kHz to 1.5 MHz

Integrated Phase Noise

(Common Clock

Architecture)

JRMS-CC

0.165

1.0

psRMS PCIe Gen 3.0

JRMS-DCHF

0.561

4.0

PCIe Gen 2.1

1.5 MHz to Nyquist

JRMS-DCLF

1.778

7.5

psRMS

PCIe Gen 2.1

10kHz to 1.5 MHz

Integrated Phase Noise

(Data Clock Architecture)

JRMS-DC

0.147

1.0

psRMS PCIe Gen 3.0

Moisture Sensitivity Level

MSL 1 – 14 QFN

MSL 3 – 16 TSSOP

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