AM79C30AVC datasheet(40/101 Pages) AMD

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Am79C30A/32A Data Sheet

set and an interrupt is generated when the last byte of

the associated packet is read from the D-channel Re-

ceive buffer.

The incoming bit stream (including FCS) is run through

the FCS generation and compare block. Upon receipt

of the closing flag, the result is checked and must be

(MSB first) 0001110100001111. Any other pattern indi-

cates an FCS error, and DER bit 3 is set to a logical 1

when the last byte of the associated packet is read from

the D-channel Receive buffer.

The DLC receiver does not assume the packet to be

byte-aligned. The architecture supports shared flags be-

tween packets, interframe fill consisting of logical 1s

(Mark idle), and interframe fill consisting of flags (Flag

idle). Mark idle is defined as at least 15 or more contig-

uous 1s. Flag idle is defined as more than two consecu-

tive flag characters, not including a closing flag. DSR2 bit

5 is set to a logical 1 while Mark idle is being detected.

DSR2 bit 6 is set to a logical 1 while Flag idle is being de-

tected. The receiver D-channel packet can be aborted at

any time during reception by setting INIT bit 6.

Transmitting D-Channel Packets

The DLC Transmitter is activated when the MSB (sec-

ond byte) of the 16-bit D-channel Transmit Byte Count

Next, the LIU starts counting the number of consecu-

tive 1s on the E-channel until the number of 1s defined

by the LIU priority mechanism is detected. After the se-

quence of 1s, the DLC transmitter will begin packet

transmission.

Address bytes for a transmit packet can be handled in

two ways: they can be loaded into the transmit buffer or

loaded into the Transmit Address Register (TAR).

There is one 16-bit TAR which can be loaded by the mi-

croprocessor. The bytes loaded into the TAR are trans-

mitted LSB first followed by MSB. For LAPD operation,

the LSB contains the SAPI, and the MSB contains TEI.

This 16-bit address (loaded LSB first) is transmitted

within the address field of the D-channel packet if en-

abled by setting DMR1 bit 2 to a logical 1. If the TAR is

enabled, the DTCR should be loaded with the number

of bytes to be transmitted excluding the address, flags,

and FCS. If the TAR is disabled, the DTCR should be

loaded with the number of bytes to be transmitted ex-

cluding the flags and FCS, and the microprocessor

must load the address to be transmitted as the first two

bytes of the D-channel packet data.

The DLC issues an interrupt when a position is

avail-able in the D-channel Transmit buffer. This inter-

rupt can be disabled by setting DMR3 bit 5 to a logical

0. The DLC also issues an interrupt to the microproces-

sor to request D-channel data bytes when the D-chan-

nel Transmit buffer empties to the threshold specified in

the D-channel FIFO mode register. This interrupt can

be disabled by setting DMR1 bit 0 to a logical 0.

If the D-channel Transmit buffer is empty, the micropro-

cessor has up to 375 ms to respond to the D-channel

transmit buffer interrupt. If the microprocessor fails to

load the data bytes in this time frame, an underrun inter-

rupt is generated in DER bit 7, and packet transmission

is terminated with a transmitted abort. The Underrun in-

terrupt can be masked by setting DMR2 bit 7 to a logical

0. Transmission is also terminated when a collision is de-

tected or LIU loss of synchronization occurs.

The D-channel Transmit Byte Count Register is decre-

mented each time a byte of data is transferred from the

D-channel Transmit buffer to the DLC. The count repre-

sents the number of bytes left to be transferred, exclud-

ing the FCS and flags. If the transmit abort bit (INIT bit

7) is set, the transmit byte count is frozen and indicates

the number of bytes left to transfer, not the number of

bytes transmitted. The last byte of the packet is deter-

mined by the D-channel Transmit Byte Count decre-

menting to zero. When this occurs, DSR2 bit 3 is set to

a logical 1.

After the last byte of the packet is transmitted, the DLC

adds the FCS and closing flag. Then the DLC issues an

interrupt (bit 6 of DSR1) to signify the end of the packet

transmission. This interrupt can be masked by setting

DMR3 bit 1 to a logical 0, and is reset either by reading

DSR1 or when the D-channel Transmit Byte Count

Once the D-channel Transmit Byte Count has decre-

mented to 0, a second packet may be loaded into the

D-channel Transmit FIFO. If the MSB of the D-channel

Transmit Byte Count Register is loaded prior to the

end-of-transmit packet interrupt, the second packet is

transmitted back-to-back with the previous packet. The

End-of-Transmit Packet interrupt is not set between the

two packets. If the MSB of the D-channel Transmit Byte

Count Register is loaded after the end-of-packet inter-

rupt, the second packet is transmitted once the LIU pri-

ority mechanism has been resatisfied.

Collision Detection

The Network Term inator echoes the transmitted

D-channel data back to the DLC in the E-channel bits

of the S-interface frame. If there is a difference between

the data transmitted and the data echoed back, a colli-

sion has occurred. The DLC alerts the microprocessor

to this event by asserting the interrupt line (INT) and

setting DER bit 2. If a collision occurs during the trans-

mission of an abort sequence, the interrupt is still is-

sued. The collision detect interrupt can be masked by

setting DMR2 bit 2 to a logical 0.

AM79C30AVC Datasheet(PDF) 40 Page - Advanced Micro Devices

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