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AM79C30AVC Datasheet(PDF) 85 Page - Advanced Micro Devices |
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AM79C30AVC Datasheet(HTML) 85 Page - Advanced Micro Devices |
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85 / 101 page ![]() Am79C30A/32A Data Sheet 85 Figure 35. SBP Mode Timing Figure 36. SBP Mode MCLK/SCLK/SFS Timing 09893H-27 SCLK Ta Tb Tp SBIN or SBOUT SFS Bd Be Bf T1 T1 Notes: 1. For PPCR2(0) = 0, SBIN data is sampled on the rising edge of SCLK; SBOUT data is changed on the falling edge of SCLK. For PPCR2(0) = 1, SBIN data is sampled on the falling edge of SCLK; SBOUT data is changed on the rising edge of SCLK. 2. T1 width is eight SCLK periods. BCL/CH2STRB MCLK (6.144 MHz) SCLK (192 kHz) tMCSC tCHFS tCLDO tCLDO tCHFS *SFS (8 kHz) SBOUT SBIN tDICH tCHDZ Notes: 1. CH2STRB timing is identical to SFS timing but delayed by eight SCLK cycles. 2. This timing diagram reflects SCLK for PPCR2(0) = 0. For PPCR2(0) = 1, the diagram is identical except that the SCLK waveform should be inverted. 09893H-28 |
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