AS5130_07 datasheet(26/42 Pages) AMSCO

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AS5130

Datasheet - Detailed Descr i pti on

Figure 19. Wake Up Signal Flowchart

Figure 21 shows the behavior of the wake up signal. The wake up signal will be low for twakeup = 10us. After that, the wake up signal will go to tri-

state condition. In case of an angle comparison with a result below the threshold, the signal will remain in tri-state condition. After switching on

VDD, the system needs max. 250us to generate an angle with maximum accuracy. A WAKE signal cannot be expected until the end of this

period.

WAKE Interface. An open drain NMOS structure is used in the WAKE pad. In order to generate a clear output signal level, a pull up resistor is

required. The pad can drive 4mA.

Figure 20. WAKE Output Pin

VDD on (fast)

store_ok

POR

reset & reset_storage

reset digital core only

Retrieve values from storage registers

WAKE (26 clk periods)

Wait (162 clks - 86us ... 95us)

Compare mode

WAKE_ON

Normal mode

store_ok ?

Copy to Storage

Normal mode

OTP readout (46bit - 140us ... 400us)

true

false

WAKE (20 clk periods)

command rst_otp

OTP readout (OTP <8> = HI

measured –

stored| >

threshold

pull up

resistor

WAKE

PAD

AS5130

VDD

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