UPD65 datasheet(26/64 Pages) NEC

26 / 64 page

µPD64A, 65

Data Sheet U14380EJ2V0DS00

6. RESET

The system reset takes effect by means of the causes as follows:

• When the POC circuit has detected low-power voltage

• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed

• When the accumulator is 0H when the RLZ instruction is executed

• When stack pointer overflows or underflows

Table 6-1. Hardware Statuses after Reset

Hardware

• Resetting by Internal POC Circuit in Operation

• Resetting by the Internal POC Circuit during

• Resetting by Other FactorsNote 1

STANDBY Mode

PC (11 bits)

000H

SP (1 bit)

Data

R0 = DP

000H

memory

R1-RF

Undefined

Previous status retained

Accumulator (A)

Undefined

Status flag (F)

Carry flag (CY)

Timer (10 bits)

000H

Port register

FFH

×××× 11×1BNote 2

Control register P3

03H

26H

Notes 1. The following resets are available.

• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

• Reset when executing the RLZ instruction (when A = 0)

• Reset by stack pointer’s overflow or underflow

2. Refers to the value by the KI or S2 pin status.

In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when

POC is released due to supply voltage startup.

UPD65 Datasheet(PDF) 26 Page - NEC

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