UPD65 datasheet(50/64 Pages) NEC

50 / 64 page

µPD64A, 65

Data Sheet U14380EJ2V0DS00

AC Characteristics (TA = –40 to +85

°C, VDD = 2.0 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Command execution time

tCY

7.9

µs

KI, S0, S1, S2 high-level

µs

width

When releasing STANDBY mode

In HALT mode

µs

In STOP mode

Note

µs

Note 10 + 52/fX + oscillation growth time

Remark tCY = 64/fX (fX: System clock oscillator frequency)

POC Circuit (TA = –40 to +85

°C)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

POC-detected voltageNote

VPOC

1.85

2.0

Note Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal reset

is released.

From the time of VPOC

≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the period

of VPOC

≥ VDD lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillation Circuit Characteristics (TA = –40 to +85

°C, VDD = 2.0 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Oscillator frequency

2.4

3.64

8.0

MHz

(ceramic resonator)

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