Power supplies and reset sources of the STM32F030 family

AN4325

10/27

DocID024966 Rev 1

1.2.2

System reset

A system reset sets all registers to their reset values, except the reset flags in the clock

controller CSR register and the registers in the RTC domain. A system reset is generated

when one of the following events occurs:

1.

A low level on the NRST pin (external reset).

2.

System window watchdog event (WWDG reset).

3.

Independent watchdog event (IWDG reset).

4.

A software reset (SW reset).

5.

Low-power management reset.

6.

Option byte loader reset.

7.

Power reset

The reset source can be identified by checking the reset flags in the Control/Status register,

RCC_CSR.

The RESET service routine vector is fixed at address 0x0000_0004 in the memory map.

The system reset signal provided to the device is output on the NRST pin. The pulse

generator guarantees a minimum reset pulse duration of 20 μs for each internal reset

source. In the case of an external reset, the reset is generated while the NRST pin is

asserted low.

Figure 4. Simplified diagram of the reset circuit

Software reset

The SYSRESETREQ bit in Cortex-M0 Application Interrupt and Reset Control Register

reference manual for more details.