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ML6430 Datasheet(PDF) 7 Page - Micro Linear Corporation |
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ML6430 Datasheet(HTML) 7 Page - Micro Linear Corporation |
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7 / 33 page ![]() ML6430/ML6431 7 Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Parameter is Luma dependent. Note 3: Reclock time after bounce. Note 4: Net phase error for single isolated missing H pulse. Note 5: Net phase error for glitch at sync level <50ns. SERIAL BUS LOGIC (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS SYSTEM TIMING (Continued) Wait Time From STOP to START On SDATA (tWAIT) 1.3 µs Hold Time for START On SDATA (tHD/START) 0.6 µs Setup Time for START On SDATA (tSU/START) 0.6 µs Min LOW Time On SCLK (tLOW) 1.3 µs Min HIGH Time On SCLK (tHI) 0.6 µs Hold Time On SDATA (tHD/DATA) 5.0 µs Setup Time On (tSU/DATA) Fast mode (Note 2) 100 ns Slow mode (Note 2) 250 ns Rise Time for SCLK & SDATA (tLH) 30 300 ns Fall Time for SCLK & SDATA (tHL) 30 300 ns Setup Time for STOP On SDATA (tSU/STOP) 0.6 µs Figure 1. Line Rate Waveforms tHEQW COMPOSITE VIDEO IN PIN 6 REGENERATED CSYNC PIN 26 EQUALIZERS SERRATIONS HBLANK PIN 25 SCLAMP PIN 28 BGATE PIN 27 BCLAMP PIN 27 HRESET PIN 23 tHBLK tHBLKW tHRW tHSW tHSERRW tHSTC tHBPCW tHBPGW tHBPC tHSTCW NOTE: NOT TO SCALE |
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