M35B32 datasheet(11/44 Pages) STMICROELECTRONICS

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DocID18391 Rev 4

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M35B32

SPI modes

Figure 4. Bus master and memory devices on the SPI bus

Note:

The /W and /RESET inputs are CMOS inputs and have also to be driven high or low if/when the SPI

bus master leaves the lines in high impedance. This has to be done with the help of pull up or pull

down resistors (depending on the application requirements).

Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only

one device is selected at a time, so only one device drives the Serial Data Output (Q) line at

a time, the other devices are high impedance.

A pull-up resistor connected on each /S input (represented in Figure 4) ensures that each

slave device on the SPI bus is not selected if the bus master leaves the /S line in the high

impedance state.

In applications where the bus master might enter a state where all inputs/outputs SPI lines

are in high impedance at the same time (for example, if the Bus Master is reset during the

transmission of an instruction), the clock line (C) must be connected to an external pull-

down resistor so that, if all inputs/outputs become high impedance, the C line is pulled low

(while the S line is pulled high). This ensures that S and C do not become high at the same

time, and so, that the tSHCH requirement is met.

M35B32 Datasheet(PDF) 11 Page - STMicroelectronics