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M35B32 Datasheet(PDF) 34 Page - STMicroelectronics

Part # M35B32
Description  32 Kbit, 256-byte page, fast program EEPROM memory accessed by SPI bus interface
PDF  44 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M35B32 Datasheet(HTML) 34 Page - STMicroelectronics

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DC and AC parameters
M35B32
34/44
DocID18391 Rev 4
Table 11. AC characteristics
Test conditions specified in Table 6 and Table 8
Symbol
Alt.
Parameter
Min.
Max.
Min.
Max.
Unit
VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V
fC
fSCK Clock frequency
D.C.
10
D.C.
20
MHz
tSLCH
tCSS1 S active setup time
30
-
15
-
ns
tSHCH
tCSS2 S not active setup time
30
-
15
-
ns
tSHSL
tCS
S deselect time
40
-
20
-
ns
tCHSH
tCSH S active hold time
30
-
15
-
ns
tCHSL
-S not active hold time
30
-
15
-
ns
tCH(1)
tCLH Clock high time
40
-
20
-
ns
tCL(1)
tCLL
Clock low time
40
-
20
-
ns
tCLCH(2)
tRC
Clock rise time
-
2
-
2
µs
tCHCL(2)
tFC
Clock fall time
-
2
-
2
µs
tDVCH
tDSU Data in setup time
10
-
5
-
ns
tCHDX
tDH
Data in hold time
10
-
10
-
ns
tSHQZ(2)
tDIS
Output disable time
-
40
-
20
ns
tCLQV(3)
tV
Clock low to output valid
-
40
-
20
ns
tCLQX
tHO
Output hold time
0
-
0
-
ns
tQLQH(2)
tRO
Output rise time
-
40
-
20
ns
tQHQL(2)
tFO
Output fall time
-
40
-
20
ns
tRLRH(2)
tRST Reset pulse width
10
-
10
-
µs
tRHSL
tREC Reset recovery time
-
3
-
3
µs
tSHRH
-
Chip should have been deselected before
Reset is de-asserted
10
-
10
-
ns
tWHSL
-
Write Protect setup time
50
-
50
-
ns
tSHWL
-
Write Protect hold time
100
-
100
-
ns
tPW
-
Page Write cycle time
-
5
-
5
ms
tPP
-
Page Program cycle time
-
5
-
5
ms
tFP
-
Fast Page Program cycle time (when
addressing the Event sector)
-1
-
1
ms
tPE
-
Page Erase cycle time
-
5
-
5
ms
tSE
-
Sector Erase cycle time
-
5
-
5
ms
tW
-
Write to Status Register cycle time
-
5
-
5
ms
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max).
2. Value guaranteed by characterization, not 100% tested in production.
3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be
equal to (or greater than) tCLQV; in all other cases, tCL must be equal to (or greater than) tCLQV+tSU.



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