AD9993BBCZ datasheet(32/56 Pages) AD

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AD9993

Data Sheet

Rev. A | Page 32 of 56

POWER MODE CONTROL REGISTER

Address: 0x008, Reset: 0x55, Name: POWER_MODES

Table 15. Bit Descriptions for POWER_MODES

Bits

Bit Name

Description

Reset

Access

PDWN_PIN_FUNC

Power-down pin function. External power-down pin mode.

0x0

0 = assertion of external power-down pin (PDWN) causes chip to enter full

power-down mode.

1 = assertion of external power-down pin (PDWN) causes chip to enter

standby mode.

CLKGEN_PDWN

Clock generation power-down mode.

0x1

[5:4]

SYNTH_PDWN_MODE

Synthesizer power-down mode.

0x1

[3:2]

DAC_PDWN_MODE

DAC power-down mode.

0x1

[1:0]

ADC_PDWN_MODE

ADC power-down mode. (ADC indexed)

0x1

00 = normal mode (power up).

01 = power-down mode; digital datapath clocks disabled; digital datapath

held in reset; outputs disabled.

10 = standby mode; digital datapath clocks disabled; outputs disabled.

11 = reserved.

ALIGN ADC LVDS CLOCKS, ADC FIFO, DAC FIFO REGISTER

Address: 0x00A, Reset: 0x80, Name: ALIGN

Table 16. Bit Descriptions for ALIGN

Bits

Bit Name

Description

Reset

Access

[7:5]

RXFIFO_WR_OFFSET

The distance of Rx FIFO write pointer away from read pointer; needs

RXFIFO_ALIGN_REQ asserted to apply this value to datapath.

0x4

RXFIFO_ALIGN_REQ

Align Rx FIFO read and write pointers.

0x0

LVDS_DCO_SYNC

Sync LVDS Tx DCO with data and strobe (self clear with following SPI clock).

0x0

TXFIFO_ALIGN

Align Tx FIFO read and write pointers (self clear with following SPI clock).

0x0

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