AD9993BBCZ datasheet(16/56 Pages) AD

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AD9993

Data Sheet

Rev. A | Page 16 of 56

THEORY OF OPERATION

PRODUCT DESCRIPTION

Figure 1 shows a block diagram of the MxFE. This product

integrates four 14-bit ADCs and two 14-bit DACs. The DAC

data interface consists of six DDR LVDS data lanes for each

DAC and a shared DCI_P/DCI_N clock (hereafter referred to

as DCI). The ADC data interface consists of four DDR LVDS

data lanes for each ADC with a shared DCO_P/DCO_N clock

(hereafter referred to as DCO) and a shared STROBE output.

The MxFE control and status registers are written/read via an

SPI interface. ADC and DAC datapaths include FIFO buffers to

absorb phase differences between LVDS lane timing and the

data converter sampling clocks. Internal AD9993 clock signals

can be developed from an external clock signal or from the

output of an on-chip PLL frequency multiplier driven by an

external reference oscillator.

SPI PORT

The AD9993 provides a 4-wire synchronous serial communica-

tions SPI port that allows easy interfacing to ASICs, FPGAs, and

industry-standard microcontrollers. The interface facilitates

read/write access to all registers that configure the AD9993. Its

data rate can be up to 25 MHz.

SPI Port Signals

SPI_SCLK (serial clock) is the serial shift clock. The serial clock

pin synchronizes data to and from the device and runs the

internal state machines. All address and input data bits are

sampled on the rising edge of SPI_SCLK. All output data is

driven out on the falling edge of SPI_SCLK.

SPI_CS (chip select) is an active low control signal used by the

SPI master to select the AD9993 SPI port. When SPI_CS is

high, SPI_SDO is in a high impedance state. During the

communication cycle, chip select must remain low.

SPI_SDI (serial data input) is the address and data input,

sampled on the rising edge of SPI_SCLK.

SPI_SDO (serial data output) is the data output pin. Data is

shifted out on the falling edge of SCLK

Figure 20 shows a timing diagram for a single byte MSB first

AD9993 SPI write operation. Each AD9993 register address is

an 8-bit value. During the first SPI_SCLK cycle, SPI_SDI = 0,

indicating that the operation is a data write. SPI_SDI is always

held low for the next two clock cycles. The next 13 clock cycles

are the first register address. The next eight clock cycles contain

data to be written. The write operation ends when SPI_CS goes

high. In this example, data for one 8-bit register is written.

Multiple registers can be written in a single write operation by

keeping SPI_CS low for multiple byte periods. The register

address is automatically updated using an address counter as

bytes are written while SPI_CS remains low.

Figure 21 depicts an MSB first register read operation. Register

data from the AD9993 appears on SPI_SDO starting on the

SPI_SCLK cycle following the last bit of the 16-bit instruction

header on SPI_SDI. Multiple registers can be read in a single

read operation by keeping SPI_CS low for multiple byte

periods.

Figure 20. 4-Wire SPI Interface Timing, MSB First Write

Figure 21. 4-Wire SPI Interface Timing, MSB First Read

SPI_CS

SPI_SCLK

A12 A11 A11 A9 A8

16-BIT INSTRUCTION HEADER

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

DON’T CARE

R/W

SPI_SDI

SPI_SDO

D7 D6 D5 D4 D3 D2 D1 D0

SPI_CS

SPI_SCLK

A12 A11 A11 A9 A8

16-BIT INSTRUCTION HEADER

A7 A6 A5 A4 A3 A2 A1 A0

DON’T CARE

R/W

SPI_SDI

SPI_SDO

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