AD9985SLASHPCB datasheet(22/32 Pages) AD

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AD9985

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Clamp Input Signal Source

This bit determines the source of clamp timing.

Table 21. Clamp Input Signal Source Settings

Clamp Function

Function

Internally Generated Clamp Signal

Externally Provided Clamp Signal

A 0 enables the clamp timing circuitry controlled by

clamp placement and clamp duration. The clamp

position and duration is counted from the leading

edge of Hsync.

A 1 enables the external CLAMP input pin. The three

channels are clamped when the CLAMP signal is

active. The polarity of CLAMP is determined by the

Clamp Polarity bit (Register 0FH, Bit 6).

The power-up default value is Clamp Function = 0.

Clamp Input Signal Polarity

This bit determines the polarity of the externally

provided CLAMP signal.

Table 22. Clamp Input Signal Polarity Settings

Clamp Function

Function

Active Low

Active High

Logic 1 means that the circuit will clamp when

CLAMP is low, and it will pass the signal to the ADC

when CLAMP is high.

Logic 0 means that the circuit will clamp when

CLAMP is high, and it will pass the signal to the ADC

when CLAMP is low.

The power-up default value is Clamp Polarity = 1.

Coast Select

This bit is used to select the active Coast source. The

choices are the Coast Input pin or Vsync. If Vsync is

selected, the additional decision of using the Vsync

input pin or the output from the sync separator needs

to be made (Register 0E, Bits 1, 0).

Table 23. Power-Down Settings

Select

Result

Coast Input Pin

Vsync (See above Text)

Coast Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Coast signal going

into the PLL.

Table 24. Coast Input Polarity Override Settings

Override Bit

Result

Determined by Chip

Determined by User

The default for coast polarity override is 0.

Coast Input Polarity

This bit indicates the polarity of the Coast signal that

is applied to the PLL COAST input.

Table 25. Coast Input Polarity Settings

Coast Polarity

Function

Active Low

Active High

Active Low means that the clock generator will ignore

Hsync inputs when Coast is low, and continue

operating at the same nominal frequency until Coast

goes high.

Active High means that the clock generator will ignore

Hsync inputs when Coast is high, and continue

operating at the same nominal frequency until Coast

goes low.

This function needs to be used along with the Coast

Polarity Override bit (Bit 4).

The power-up default value is 1.

Seek Mode Override

This bit is used to either allow or disallow the low

power mode. The low power mode (Seek Mode)

occurs when there are no signals on any of the Sync

inputs.

Table 26. Seek Mode Override Settings

Select

Result

Allow Seek Mode

Disallow Seek Mode

The default for this register is 1.

PWRDN

This bit is used to put the chip in full power-down. See

the Power Management section for details of which

blocks are powered down.

Table 27. Power-Down Settings

Select

Result

Power-Down

Normal Operation

7-3

Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the

Sync-on-Green slicer to be adjusted. This register

adjusts it in steps of 10 mV, with the minimum setting

equaling 10 mV (11111) and the maximum setting

equaling 330 mV (00000).

The default setting is 23, which corresponds to a

threshold value of 100 mV; for a threshold of 150 mV,

the setting should be 18.

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