AD9985SLASHPCB datasheet(26/32 Pages) AD

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AD9985

Rev. 0 | Page 26 of 32

2-WIRE SERIAL CONTROL PORT

A 2-wire serial control interface (I2C) is provided. Up to two

AD9985 devices may be connected to the 2-wire serial interface,

with each device having a unique address.

The 2-wire serial interface comprises a clock (SCL) and a

bidirectional data (SDA) pin. The analog flat panel interface

acts as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled high by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

There are five components to serial bus operation:

•

Start Signal

•

Slave Address Byte

•

Base Register Address Byte

•

Data Byte to Read or Write

•

Stop Signal

When the serial interface is inactive (SCL and SDA are high),

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slaved devices that a data transfer sequence

is coming.

The first eight bits of data transferred after a start signal

comprise a 7-bit slave address (the first seven bits) and a single

R/W bit (the eighth bit). The R/W bit indicates the direction of

data transfer, read from (1) or write to (0) the slave device. If the

transmitted slave address matches the address of the device (set

by the state of the SA1-0 input pins in Table 42), the AD9985

acknowledges by bringing SDA low on the ninth SCL pulse. If

the addresses do not match, the AD9985 does not acknowledge.

Table 42. Serial Port Addresses

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(MSB)

DATA TRANSFER VIA SERIAL INTERFACE

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9985 does not acknowledge the master device during a

write sequence, the SDA remains high so the master can

generate a stop signal. If the master device does not acknowl-

edge the AD9985 during a read sequence, the AD9985

interprets this as “end of data.” The SDA remains high so the

master can generate a stop signal.

Writing data to specific control registers of the AD9985 requires

that the 8-bit address of the control register of interest be

written after the slave address has been established. This control

tions. The base address autoincrements by one for each byte of

data written after the data byte intended for the base address.

SDA

SCL

tBUFF

tSTAH

tDHO

tDSU

tDAL

tDAH

tSTASU

tSTOSU

Figure 12. Serial Port Read/Write Timing

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